@吳俊融北科大
Thank for your clear explanation, I learned a lot. Will the code design by finite state machine better? Because your code mixing sequential circuits and combination circuits in one block. Looking forward to your reply🥹
@thebullybuffalo
I would recommend an improvement to this code: set the shift register BACK to zero after the conversion is done in the last 'if' block shift_register [19:8] = 0; This will avoid the shift register continually continuing up to a larger and larger number every time the 8-bit number changes. This, I think, will save data/time as the number of times the <number> changes will continually increase Great video. The verbosity in your code made it easier to follow. Very clear!
@OkoIyae6
I used this algorithm successfully in verilog but when I tried adapting it to vhdl I haven't been successful, anyone know why?
@curtisnotestine3134
In the first if statement: "if (i==0 & (OLD_eight_bit_value != eight_bit_value)) begin" why do you assign the temp_* values to the upper bits of the shift_register? This is confusing. Why not assign to all 0's which is what they should be at the beginning of the binary to BCD conversion? Thank you for the tutorial!
@profsinner4613
If you could post videos about PISP, PIPO, and SIPO that would appreciated.
@mukulsharma8616
Plz make a vedio about digital alarm clock.
@sajeewadilshan
hello! could you tell me why addition by 3 is necessary for when one's, ten's or hundred's place is greater than or equal to 5?
@SimplyEmbedded
Hope you enjoyed this tutorial! Let me know what was something you learned through this video!
@asmaulhusna7079
What is the shift register value to be given for 12 bit integer?
@hardikmakwana9394
if 2's compliment 8 bit binary number is there than what changes should I do in the above code? I want to make 2's compliment 8 bit binary to BCD converter in verilog. In 2's Complement 8 bit number, MSB [bit 7] is sign bit.
@sheema_1935
do we need a testbench to run our code ?
@thebullybuffalo
it's REPresents. not REEPresents. lol 1:04 1:13
@OkoIyae6
I used this algorithm successfully in verilog but when I tried adapting it to vhdl I haven't been successful, anyone know why?
@SK17470