Samsung SAFE™ Forum - "PC Packaging: Trends in Heterogeneity and Packaging Solutions"

Cutting edge foundries are developing and shipping increasingly more powerful ICs. At the same time, IC architects and product designers face tough choices in the quest for new levels of performance at affordable price points. Increasingly, part of this calculus is growing interest in heterogeneous System-in-Package (SiP) technology in addition to the classic system on chip (SoC) designs. This packaging trend began in earnest 5 years ago and has been demonstrated with processors-high bandwidth memory (HBM) in-package combinations, now in high-volume manufacturing (HVM). Going beyond this trend, however, the first implementation of high-volume chiplet-based designs and products in the marketplace has occurred. Cost and performance balance at the 5-nm and 3-nm nodes has created growing customer interest in this approach and IC packaging has a critical role to play.

High bandwidth memory integrations provided unparalleled memory bandwidth and capacity, integrated into the IC package with 2.5D Through Silicon Via (TSV) interposer technology. This construction served to push the infrastructure in packaging and devices to deliver this approach to HVM. Now, building on that capability, a distinct move towards discrete long-reach serial/deserializer (SerDes) devices has started, obviating the need to keep the SerDes inside the rest of the SoC with chiplets integration of the logic and IO functions. This has opened up new architectural freedom with increased total gate counts, in-package memory and high-speed IO counts not achievable in other more standard approaches.

Paired with these heterogenous approaches and tighter control of a variety of operating voltages for new silicon nodes as well as previous versions, managing the power delivery network (PDN) is also becoming more demanding. Creative approaches for a local bypass to help manage the power delivery impedances are being developed in anticipation of these functional needs. Total power and power density also continue to trend upwards, requiring an enhanced thermal path. Several solutions will be discussed.

How these multiple dies communicate with one another, the number and the size of the dies, final modules and packages are co-developed with high-speed signal routing requirements and the PDN in mind. The demands on advanced IC packaging continue to increase and delivering on these capabilities is a high priority for the packaging industry and especially for Amkor.

Presenter: Mike Kelly, VP, Advanced Package & Technology Integration

Presented at Samsung SAFE™ Forum 2020