Self-Checking Testbench with readmemb (Combinational Circuit) [My HDL Workflow | Tutorial 3]

Write self-checking testbench for combinational circuit. No more verifying the output results manually by our tired eyes. The same technique can be modified to suit sequential circuit, but I'll leave that for you to figure out because it is dependent on your circuit! For example, rising-edge-triggered elements and falling-edge-triggered elements require different timing for checking the results, perhaps you can give your DUT a different clock than the clock used to load and check results.

00:00 Introduction
00:07 Create testvectors file
01:30 Create self-checking testbench (combinational circuit)
01:56 BS about code you can easily read by yourself

GitHub link: github.com/endeneer/Files-for-My-Favourite-HDL-Wor…