Applied Materials’ Chip Wiring Innovation Enables More Energy-Efficient Computing

Today’s most advanced logic chips can contain tens of billions of transistors connected by more than 60 miles of microscopic copper wiring. As chipmakers continue to shrink features with each technology generation, they must also shrink the wires, and while it may seem counterintuitive, smaller is not actually better when it comes to wiring. Narrowing the copper wires creates steep increases in electrical resistance that can reduce chip performance and increase power consumption.

To create wiring, trenches are etched into dielectric material and then lined with a thin stack of metals that typically includes a barrier layer to prevent copper from migrating into the chip, a liner to promote copper adhesion, and finally bulk copper that completes the signal wires. As chipmakers scale the wiring, the barrier and liner take up a larger percentage of the volume intended for wiring, and it becomes physically impossible to create low-resistance, void-free copper wiring in the remaining space.

Applied Materials’ latest IMS™ (Integrated Materials Solution™) combines six different technologies in one high-vacuum system, including an industry-first combination of materials that enables chipmakers to scale copper wiring to the 2nm node and beyond. The Endura™ Copper Barrier Seed IMS™ with Volta™ Ruthenium CVD creates a binary metal combination of ruthenium and cobalt (RuCo), which simultaneously reduces the thickness of the liner by 33 percent to 2nm, produces better surface properties for void-free copper reflow, and reduces electrical line resistance by up to 25 percent to improve chip performance and power consumption.

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